1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and the semiconductor device, and particularly, relates to a method for fabricating a semiconductor device in which plural transistors are integrated and the semiconductor device.
2. Description of the Related Art
Recently, as systems are diversified, a semiconductor device such as system LSI in which a digital circuit and an analog circuit are integrated in one chip is practically used. In such a semiconductor device, since the digital circuit in which reduction of leakage current during off period is primarily considered and the analog circuit in which current-driven capability is primarily considered are integrated, a threshold voltage that is the conduction starting voltage of a transistor must be changed between the digital and analog circuits. The threshold voltage is generally controlled in a chip by changing the density of impurity implantations into a diffusion region for each threshold voltage.
Alternatively, as an example of methods for changing the conduction starting voltage of the transistor, there is a CMOS transistor described in JP-A-5-335500 (FIGS. 1, 4 on pp. 3–4). In the CMOS transistor, a distance between a source contact and a gate electrode is made to be longer than a distance between a drain contact and the gate electrode in a P-type or N-type transistor or both, and a series resistance is added to the source side, thereby a parasitic transistor is made to be not connected even in the case where the same drain voltage is applied.
In the fabrication method in which the density of the impurity implantation density is changed for each threshold voltage, since a mask for ion implantation must be prepared for each threshold voltage, there is a fear of cost increases due to an increased number of the masks. Moreover, ion implantation is required for each of P-channel and N-channel. Therefore, when the threshold voltage increases, the number of the ion implantations is twice as many as the number of the increased threshold voltages is required, and thus fabrication processes increase, and there is fear of an increase of fabrication time and cost.
On the other hand, in the method described in JP-A-5-335500, the drain voltage which causes conduction of the parasitic transistor may be considered to be changed in the CMOS transistor. However, the method described in JP-A-5-335500, which is a method of preventing a positive feedback to the parasitic transistor by confining current flow into the parasitic transistor, does not change the threshold voltage of the CMOS transistor itself. In addition, when the series resistance is inserted into the source side as described in JP-A-5-335500, there is a problem that the threshold voltage increases, resulting in a decrease in operation velocity.